prakashvenugopal
Advanced Member level 1
Hi,
How to do simulation for this vhdl code using ISE 10.1.
entity counter is
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(3 downto 0));
end counter;
architecture Behavioral of counter is
signal count: std_logic_vector(3 downto 0) := "0000";
begin
process(clock)
begin
if clock ='1' and clock'event then
if enable = '1' then
count <= count + 1;
end if;
end if;
end process;
Q <= count(3 downto 0);
end Behavioral;
thanks,
V. Prakash
How to do simulation for this vhdl code using ISE 10.1.
entity counter is
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(3 downto 0));
end counter;
architecture Behavioral of counter is
signal count: std_logic_vector(3 downto 0) := "0000";
begin
process(clock)
begin
if clock ='1' and clock'event then
if enable = '1' then
count <= count + 1;
end if;
end if;
end process;
Q <= count(3 downto 0);
end Behavioral;
thanks,
V. Prakash