Regarding the simulation for the vhdl code for counter using ISE

[TrickyDicky]

add the signals to your wave window and re-run the simulation.

 

[prakashvenugopal]

Hi,

In the above test bench code mentioned in #20

in clock process part mentioned in bold character in #20:

Existing code :

constant clk_period : time := 62.5 ns;


clk_process rocess
begin
clk_in <= '0';
wait for clk_period/2; --31.25 ns
clk_in <= '1';
wait for clk_period/2; --31.25 ns
end process;

I try to change this clk_in as 3.3 us. on_time= 1.65 us and off_time= 1.65 us. for this, i changed the code as

New code:

clk_process rocess
begin
clk_in <= '0';
wait for 1.65 us;
clk_in <= '1';
wait for 1.65 us;
end process;

[/QUOTE]

There is no clock seen in the simulation wave window. will this above code is correct to generate 3.3 us clock?
Please do let me know.

Thanks,
V. Prakash