Jan 23, 2012 #1 P Padfoot3 Newbie level 5 Joined Jan 10, 2012 Messages 10 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,344 Hello, Can anyone tell me why and how to write test bench in VHDL? How is test bench different from the code for simulation?
Hello, Can anyone tell me why and how to write test bench in VHDL? How is test bench different from the code for simulation?
Jan 23, 2012 #2 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,047 Trophy points 1,393 Activity points 39,769 A test bench is code solely for simulation - you would not compile it in Quartus or ISE. You can do a lot of things you otherwise could not do for synthesisable code.
A test bench is code solely for simulation - you would not compile it in Quartus or ISE. You can do a lot of things you otherwise could not do for synthesisable code.
Jan 24, 2012 #3 H harerama Member level 4 Joined Sep 21, 2011 Messages 79 Helped 2 Reputation 4 Reaction score 2 Trophy points 1,288 Location Bangalore,India Activity points 1,747 Check below link for how to write testbench code VHDL coding tips and tricks: How to write a testbench?
Check below link for how to write testbench code VHDL coding tips and tricks: How to write a testbench?