regarding task call in verilog

[sumanthhv]

dear forum members.

i've defined a task like this :

task my_task;
input x,y;
begin
$display("task my_task called")
wait(x)
if (~y)
begin
$display("both x and y must be high at all times");
$finish;
end
$display("normal exit");
endtask

in my main testbench i'm calling the task like this:

module my_tb;
.
.
.
.
always
begin
my_task(w,z)
end
.
.
initial
.
.
.
$finish;
.
.
.
endmodule

the simulator prints "task my_task called" once and exits via $finish in my_tb. But when i modified the task like this things worked as expected:

task my_task;
input x,y;
begin
$display("task my_task called")
wait(my_tb.w)
if (~my_tb.z)
begin
$display("both x and y must be high at all times");
$finish;
end
$display("normal exit");
endtask

this solution looks crude and clumsy to me. Why aren't parameters getting passed properly? i tried declaring the task as automatic, to no avail.

Thanks in advance,
Sumanth

 

[kornukhin]

Try this:

task my_task(input x, y);
reg x,y;

 

[sumanthhv]

Try this:

task my_task(input x, y);
reg x,y;

kornukhin,

Thanks for replying. I tried your soultion. But, the same problem persists.

thanks,
sumanth