Regarding SystemVerilog support in Modelsim SE

[delon]

Hello All, I am using modelsim tools for compiling and debugging RTL for the first time. However I used VCS before.

I have access to Modelsim SE 5.8e. Does anyone know if it supports SystemVerilog features for Design and *Validation* ? I am not sure if it fully supports *SystemVerilog for Validation*. If no, then I would appreciate if anyone can suggest me any other validation methodology which can be used to validate my RTL design.

Thanks in advance.

 

[dave_59]

Modelsim support most of SystemVerilog except for randomization, functional coverage, and assertions. However, that version of Modelsim is so old, and SystemVerilog was so new at the time that not much is supported.

 

[delon]

Modelsim support most of SystemVerilog except for randomization, functional coverage, and assertions. However, that version of Modelsim is so old, and SystemVerilog was so new at the time that not much is supported.

Thanks a lot for your input. I can do all my RTL coding in verilog. I was mostly interested to use SystemVerilog to build the verification/validation infrastructure. I can always use C/C++ to build the software model but I am not sure how to interface them with verilog code and do stress test the hardware to get 100% coverage . Any suggestion regarding this ?

I used SystemVerilog for validation before to validate some RTL cores and really liked it's validation features. I am a newbie in this sort of work. So, any advice/suggestion will be highly appreciated.