Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Regarding Sample & Hold

Status
Not open for further replies.
C

coolstuff07

Advanced Member level 4
Joined
Mar 9, 2008
Messages
118
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,298
Activity points
1,949
Dear,

Iam designing differential sample & Hold amplifier for 14-bit pipelined ADC with sampling speed of 150Msps. If i consider coherent sampling method for sample & Hold circuit also. How many samples i should consider for one cycle input signal during dft analysis.

Bye.
 

You should consider 2power14 (16384) samples.
What kind of opamp are you going to use and what is the supply voltage ?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top