Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Usually power consumption of CMOS analog circuit is calculated with multiflying current and voltage. Bipolar will consume more than CMOS according to base driving.
For digital, surely CMOS is much lower in power consumption than bipolar.
But for analog, it depends. Even though bipolar draws base current, so does the collector or the drain of a MOS transistor. So there is always static power dissipation. Bipolar gives you much higher transconductance of the same current as compared to a MOS transistor. So when designing RF circuits, bipolar can be used to design much higher frequency circuits than CMOS. Even for normal analog operations, bipolar are considered to have lower noise. The only place where I think CMOS is much better than bipolar is low-power analog. Here the devices are operated in sub-threshold. I have not seen any work on ultra-low power analog in bipolar.
The cmos static power consumption is very less and hence is used for logic implementation. However in design of analog, the biasing current flows in cmos as well as bipolar and will mostkly be governed by the design specs.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
