regarding number LUTs and SLICES????

[me0414013]

SIR i tried to implement triple modular reduntant mux4:1... but after repeating the hardware 3 times and passing it through voter also its showing the same number of slices and luts... why is it happening so...? is it all because of rooting algorithm????or is it minimizing the logic...? (since i have to compare area*time for the two muxes)

 

[shaiko]

I think it simply optimizes the redundant logic away...
What HDL are you using ?

 

[mrflibble]

As shaiko said, this very much sounds like optimization. You'll have to take a look at using SAVE and KEEP constraints to prevent this.

 

[me0414013]

thank u... Iam using VHDL

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As shaiko said, this very much sounds like optimization. You'll have to take a look at using SAVE and KEEP constraints to prevent this.

Sir can u brief SAVE and KEEP constraints. thank u for ur reply

 

[mrflibble]

The constraints user guide contains all sorts of fun information on precisely this: https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/cgd.pdf

 

[K-J]

SIR i tried to implement triple modular reduntant mux4:1... but after repeating the hardware 3 times and passing it through voter also its showing the same number of slices and luts... why is it happening so...? is it all because of rooting algorithm????or is it minimizing the logic...? (since i have to compare area*time for the two muxes)

Does it simulate correctly? If not, then get that working correctly. Asking about optimization on something that is not functionally correct is a meaningless exercise.

Kevin Jennings

 

[me0414013]

Does it simulate correctly? If not, then get that working correctly. Asking about optimization on something that is not functionally correct is a meaningless exercise.

Kevin Jennings

Sir, This is my VHDL code for Triple modular redundant MUX.
Is it correct sir?

_____________________________________________________
entity mux4_1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
s1 : in STD_LOGIC;
s2 : in STD_LOGIC;
o : out STD_LOGIC);
end mux4_1;

architecture Behavioral of mux4_1 is
signal o1,o2,o3:std_logic;
begin
process(a,b,c,d,s1,s2)
begin
o1<=(a and (not s1 and not s2)) or (b and (not s1 and s2))--repeating the hardware;
or (c and (s1 and not s2)) or (d and(s1 and s2));
o2<=(a and (not s1 and not s2)) or (b and (not s1 and s2))
or (c and (s1 and not s2)) or (d and(s1 and s2));
o3<=(a and (not s1 and not s2)) or (b and (not s1 and s2))
or (c and (s1 and not s2)) or (d and(s1 and s2));
o<= (o1 and o2) or(o2 and o3)or (o1 and o3);-- voting mechanism;
end process;
end Behavioral;
______________________________________________________________

 

[mrflibble]

Is it correct sir?

Can you show us the testbench code + results? If not, please make it so.

 

[FvM]

It's clear that the redundancy will be completely removed by the design compiler unless you enforce a different behaviour by respective synthesis attributes. Even keeping the intermediate outputs o1..o3 by a synthesis attribute might be insufficient to achieve actual redundancy.

Technically, I doubt that the redundancy makes much sense beacuse you can construct many kinds of device failures that dwarts it.

 

[K-J]

Sir, This is my VHDL code for Triple modular redundant MUX.

It's not redundant since any synthesis tool will see that the logic for 'o1', 'o2' and 'o3' are all the same, therefore it only needs to implement one of them. That will then cause the equation for 'o' to reduce accordingly. The expected result would then be the same whether you implement this one time or three times, which is what you said was happening.

Since the inputs to the design (a, b, s1 and s2) are not redundant, there is no reason to expect what you have implemented to have any actual redundancy. Make those inputs redundant and you'll get three sets of logic. However, then you'll have to contend with the fact that you're implementing this redundant scheme inside a single device which is inherently not redundant (i.e. the single bitstream that loads the FPGA, the single power supply, the single laminate, etc.)

Kevin Jennings

 

[FvM]

It's not redundant since any synthesis tool will see that the logic for 'o1', 'o2' and 'o3' are all the same.

Literally, any logic that is removed during optimization can be designated redundant, I think. But I completely agree that no functional redundancy is implemented by the design.