I designed a LDo votage regulator with input voltage of 1.8 V and 100mA load in 180 nM tech. in cadence. I am getting all the parameters like Load regulation, slew rate, dropout voltage, Iq very accurate. but iam not getting line regulation. if i change the input voltage, output also changing (Drop is constant).
It´s impossible to give a good answer with the given informations.
What is the expected output voltage?
How do you regulate the output voltage?
Do you have enough headroom? What´s the expected (calculated) dropout voltage with full load?
It´s impossible to give a good answer with the given informations.
What is the expected output voltage?
How do you regulate the output voltage?
Do you have enough headroom? What´s the expected (calculated) dropout voltage with full load?
my expected output is 1.7 volts. at full load of 100mA i got dropout voltage of 85mV. I got perfect load regulation but not line regulation. i am attaching schematic of LDO for your reference
Is the LDO error amp a differential pair + output stage, and is that supplied by the main input supply, or does it have it's own (Bandgap) reference and supply (the internal LDO to power the external LDO...)? Without a reliable "inner guts" supply voltage the line regulation will follow the input supply, assuming the MOSFET isn't the wrong way round - easy to do by mistake .