Regarding insertion Delay and Skew

[Manochitra]

hi.....

For an iteration we haven 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why?

 

[yadavvlsi]

You need to look on your skew histogram. If you have few paths in 0.100ns to 0.250ns. It is better to go for '0.29ns insertion delay and 0.25 skew'. If you have less insertion delay, you will gain a lot in OCV.

 

[venkatramanan]

how insertion delay depends on ocv?how we will get gain in ocv... can u explain ple...i got confusion

 

[yadavvlsi]

On chip variation is taken care by applying derates in clock and datapath. Normally in our design we apply 8-10 % derate in clock path. This means reported cell delay will be actual cell delay + 10 % of actual cell delay. If your insertion delay is high then your derate factor in delay will also high. This will directly effect your timing.