Regarding help in instantiating Xilinx IP CORE GENERATOR in verilog

[vivek keviv]

Hi,

I am working with USRP-FPGA. I would like to build my own custom fpga image into my USRP-FPGA. Here my custom fpga image is Low pass FIR filter. when I tried to wirte and synthesize my low pass filter verilog code with Xilinx IP core generator, it shows some XST tool warnings something like ip core didnot attach... due to this I could not able to receive my signal spectrum. I have shown the warnings below with this post.

Can you please kindly advise me regarding this warnings.. note: Low Pass Filter without IP CORE gives output.

WARNING:Xst:2211 - "ipcore_dir/my_FIFO.v" line 64: Instantiating black box module <my_FIFO>.
WARNING:Xst:2211 - "ipcore_dir/mac_i.v" line 75: Instantiating black box module <mac_i>.
WARNING:Xst:2211 - "ipcore_dir/mac_q.v" line 85: Instantiating black box module <mac_q>.
WARNING:Xst:616 - Invalid property "SYN_BLACK_BOX 1": Did not attach to my_mac_i.
WARNING:Xst:616 - Invalid property "SYN_NOPRUNE 1": Did not attach to my_mac_i.
WARNING:Xst:616 - Invalid property "SYN_BLACK_BOX 1": Did not attach to my_mac_q.
WARNING:Xst:616 - Invalid property "SYN_NOPRUNE 1": Did not attach to my_mac_q.

 

[mrflibble]

As a first rule of thumb, you can ignore those warning because they are just that ... warnings. Your design should still work.

If you really want to know (not a bad habit at all), then usually copy/paste a specific error message into google has pretty good chances of giving you some idea.I think that in this particular case the messages pretty much speak for themselves. For some extra information you could those three *.v files.

 

[vivek keviv]

Hi

Thanks for your valuable time.

Without using Xilinx IP Core module, I can able to get the results but when i try to instantiate IP core with my verilog LPF code I couldn't able to get the results.

I believe that there may be some problem due to this XST 616 warnings. I have googled this warnings with the intention of solving but I couldn't able to get the proper solution to this warnings.

My design works perfect when the absence of xilinx IP core. So the problem must be with the Xilinx IP core module. It synthesize well the only reason why it doesn't give output is because of these warnings as i believe.

Is there any solution to this warnings???

 

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