Regarding design for testability

[pavankumarmnnit]

hi , i want to know whether synopsys tetramax can be used after design compiler directly.

i.e without including placement,routing tools like astro and jupiter.

My project needs to have design for testability included in it.

 

[viju]

Yes. You can start parallely generation of ATPG. No need to wait till P&R.
I belive this is a standard practice.

 

[pavankumarmnnit]

i want to know what is the use of dft compiler ,whether it is part of design compiler or not.
I need tutorials to work on design compiler ,dft compiler and tetramax .

Could any body send the available materials.. .....plz.

 

[sunilbudumuru]

DFT compiler uses Design compiler together with the Test compiler for the test logic insertion.

Be sure about the flow first.

Design Compiler (Synthesized netlist) -> DFT Compiler (Test Logic insertion to the Synthesized netlist) -> Tetramax (ATPG vector genration to the Test logic inserted, Synthesized netlist to get the Test coverage and ATPG vectors)

Here, if u r not saticified with the coverage during ATPG, verify the test un-covered logic using the ATPG reports and again cover the test uncovered logic by test point insertion or other methods based on the situation using DFT Compiler and re-do the ATPG process.

The above process will go till u get the required coverage.

Once u got the required coverage, do the STA on the final netlist to verify whether the timing is clean (setup) and then provide it to the P&R to get the final P&R netlist.

Once the P&R is done, do the ATPG again on the final P&R netlist for sign-off coverage and the ATPG vectors.

Hope u r okay with the above expelnation.

Added after 1 minutes:

by the way i am also from MNNIT

 

[jayTudu]

Hi friend,
I want to know, whether the scan chain order will remain same for the synthesized netlist even after the P & R. I doubt becoz placement n routing tries to optimize the routing-related delay which may break the initial order of scan cells.
Actually the problem is, I have done one work on scan chain reordering just based on the netlist generated by DFT compiler. I was unware of the P & R related issue. So now I want to know the fact.

Thanks in Advance
Jay

 

[entropy]

Hi friend,
I want to know, whether the scan chain order will remain same for the synthesized netlist even after the P & R. I doubt becoz placement n routing tries to optimize the routing-related delay which may break the initial order of scan cells.
Actually the problem is, I have done one work on scan chain reordering just based on the netlist generated by DFT compiler. I was unware of the P & R related issue. So now I want to know the fact.

Thanks in Advance
Jay

Scan reorder will be done in PR step as after placement ffs locations are settled, may not be fixed but should not be changed heavily, so chain's ffs will be disordered compared to synthesis netlist.

 

[jaydip]

ATPG generated coverage and pattern it self may not remain valid after P&R, as during P&R scan re-ordering is going to happen .. so I am wondering what is the actualy flow?

1) They generate the patterns for DFT on unplaced netlist, just to have rough coverage number -> perofrm P&R -> re-order scan chain -> Regenerate patterns for new scan chains -> get "actual" coverge number

2) perform p&r -> perform scan stitching -> generate ATPG patterns -> get "actual" covergae numbers

Which one of above mentioned method is industry standard? What are pros and cons of each one? Any body ???

DFT compiler uses Design compiler together with the Test compiler for the test logic insertion.

Be sure about the flow first.

Design Compiler (Synthesized netlist) -> DFT Compiler (Test Logic insertion to the Synthesized netlist) -> Tetramax (ATPG vector genration to the Test logic inserted, Synthesized netlist to get the Test coverage and ATPG vectors)

Here, if u r not saticified with the coverage during ATPG, verify the test un-covered logic using the ATPG reports and again cover the test uncovered logic by test point insertion or other methods based on the situation using DFT Compiler and re-do the ATPG process.

The above process will go till u get the required coverage.

Once u got the required coverage, do the STA on the final netlist to verify whether the timing is clean (setup) and then provide it to the P&R to get the final P&R netlist.

Once the P&R is done, do the ATPG again on the final P&R netlist for sign-off coverage and the ATPG vectors.

Hope u r okay with the above expelnation.

Added after 1 minutes:

by the way i am also from MNNIT