DFT compiler uses Design compiler together with the Test compiler for the test logic insertion.
Be sure about the flow first.
Design Compiler (Synthesized netlist) -> DFT Compiler (Test Logic insertion to the Synthesized netlist) -> Tetramax (ATPG vector genration to the Test logic inserted, Synthesized netlist to get the Test coverage and ATPG vectors)
Here, if u r not saticified with the coverage during ATPG, verify the test un-covered logic using the ATPG reports and again cover the test uncovered logic by test point insertion or other methods based on the situation using DFT Compiler and re-do the ATPG process.
The above process will go till u get the required coverage.
Once u got the required coverage, do the STA on the final netlist to verify whether the timing is clean (setup) and then provide it to the P&R to get the final P&R netlist.
Once the P&R is done, do the ATPG again on the final P&R netlist for sign-off coverage and the ATPG vectors.
Hope u r okay with the above expelnation.
Added after 1 minutes:
by the way i am also from MNNIT