Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Regarding clock recovery?? Plz help...

Status
Not open for further replies.

rag.perfect

Member level 1
Joined
Oct 29, 2007
Messages
35
Helped
15
Reputation
30
Reaction score
8
Trophy points
1,288
Activity points
1,451
hi frnds...

i know that clock recovery is done at RX end from incoming data itself. but how a clock can be embedded into tx data at TX end??
any circuit, any info.. regarding that.... plz help....
 

The transmited data is scrambled before final modulation and transmition. Scramblers are simple circuits realised as a chain of D flip-flop cells and combined with usually 2 XOR gates.

Scrambler provides that the data is not very uniform for example "11110000". Scrambler would cause extra transitions in data so that clock and data recovery circuit can extract the clock and retime the data on the regenerated clock on receiving side. After that the received and reclocked data has to be descrambled to with descrambler to get original data "111100000" or what ever was send over transmition path.

Google for scramblers, descrambler for images an further explanations, when in doubt ask.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top