This is because, in most of the board design, FPGA reset pin is connected to a RC cirucit. When you push reset button(making short with ground), the capacitor charge is dischared to the ground, so on reset pin there will be a logic '0' (reset condition).
When you release the push button, capacitor starts chagning and subsiquently become fully charged (active high state), now reset become '1', means FPGA is out of reset.