regarding active low reset

[shivakumar043]

why preferactive low signal

Hi all,
I have seen reset pin in most of the design active low , can any one explain why they prefer active low signal.

 

[IanP]

active low reset



Regards,
IanP

 

[vs21]

active low reset?

Hi,

This is because, in most of the board design, FPGA reset pin is connected to a RC cirucit. When you push reset button(making short with ground), the capacitor charge is dischared to the ground, so on reset pin there will be a logic '0' (reset condition).

When you release the push button, capacitor starts chagning and subsiquently become fully charged (active high state), now reset become '1', means FPGA is out of reset.

Regards
vs21

 

[spauls]

If RESET is at active high than even a noise signal of small voltage level can drive it.