REG:Layout Doubts as i am new to it.

[pavan10]

Hi,

I have few doubts in layout can any body answer.

1. If we are not meeting spacing which is mentioned in DRC.

Ex:Actuall Space between to metals is 0.5, but i am maintaing only 0.3 and its send for fabrication what are the problems may occur.

2.What is the difference between Fingering and Multiplier other than gate resistance is reduced, and what about the area of drain area and source area, capacitance and if any please update it .

Accourding to me drain area will decrease and source area remain same in fingering.

3.what are the different types of resistors are available and which will be having more resistance.

4.why we go for differential amplifier Common centroid and Current mirrors Interdigitazition.

5.If i have multiple block of layout. If i wanted to execute particular block DRC and LVS living rest which settings i have to change please let me know.

6.Can any body give me fabrication Process book or PDF if any body have.

7.what is the difference between Min density and Max density.

8.How the minimum metal width is diffiend for higher technologies and lower technologies.

Thanks in advance

 

[D.A.(Tony)Stewart]

Fabrication costs rise with each supplier for lower than standard track gap widths ,thus DRC limits affect cost and yields depending on supplier capability.

https://en.m.wikipedia.org/wiki/Design_rule_checking


Similar to board layout, lithographic resolution costs,

... The geometry is optimized for best cost & reliability Design Rules from IPC standards or from supplier standards based on needs and volume product cost targets.

 

[pavan10]

Thanks for helping

 

[arunkumarshanti]

Hi
My replies are in blue.

1. If we are not meeting spacing which is mentioned in DRC.
Initially, your layout design tool signals DRC error. However if you neglect the error, after fabrication, the metal lines could have shorted. This will fail your entire chip.

2.What is the difference between Fingering and Multiplier other than gate resistance is reduced, and what about the area of drain area and source area, capacitance and if any please update it .
For ex:
1. A power transistor will have a width in the range of several mm. If you need to draw a 1mm width transistor with min. technology length, it will look like a tall thin line. I mean your chip area will be such that the vertical length will be very large (mm) compared to the horizontal length (um). Hence to avoid this, the fingers are used. It looks like a vertically long transistor is cut into several small (width) transistors & stiched horizontally. The multipliers is the exact replica of a transistor structure. 2 multiplier 2 finger means you have 2 transistor structures wherein each structure has two seperate gates. Hence the total with = 2*2*finger width.
2. A differential amplifier needs high level of matching between the differential pair (2 transistors). Hence the width of the transistor is split & matched between the 2 transistors using matching techniques.

So you can save the chip area by using the finger options since it uses merging the 2 transistors. The close proximity increases. Also it reduces the parasitics.


3.what are the different types of resistors are available and which will be having more resistance.
Resistors can be drawn using poly, all metal layers (top metal has least sheet resistance), NMOS/PMOS resistor, nwell, etc.. Nwell has highest sheet resistance.

4.why we go for differential amplifier Common centroid and Current mirrors Interdigitazition.
Interdigitization equalizes X (horizontal) process variations among the transistors but Common centroid equalizes X & Y (Horizontal & vertical) process variations. As differential amplifier need higher matching, common centroid is used.

5.If i have multiple block of layout. If i wanted to execute particular block DRC and LVS living rest which settings i have to change please let me know.
It depends on which tool you use. However in Cadence layout-XL, there is an option to select particular block for DRC. I am not sure about the partial LVS option.

6.Can any body give me fabrication Process book or PDF if any body have.
Look for the CMOS process book by peter van zant .

7.what is the difference between Min density and Max density.
I am not sure about what specifically it points to.

8.How the minimum metal width is definend for higher technologies and lower technologies.
The minimum metal width is defined by the IC foundry. The foundry develops the DRC for a particular technology. It is a protocol between the foundry & the layout designer that if the DRC is maintained, the foundry can offer error free chips. However there will be some significant number of chips that will fail due to manufacturing defect. This can be caused due to poor layout design or the errors by the foundry.

Also the metal width has to be calculated by the layout designer based on the current through a metal line & the calculated current density has to be lesser than the maximum allowed current density of a metal layer.

Regards
Arun