hcu
Advanced Member level 4
Hello all,
please suggest me a reference design on stratix 10 board with a PCIe , enabled high performance burst interface (HPTXS) port of 256 bit width.
I searched on the net to have a clear understanding about this port, but not found anything. But, there are 2 paras of information available on the user-guide that available from the tool, but didn't understood.
someone please send me a link to understand the functionality of that port, referral design.
some questions
1. can i enable this HPTXS port irrespective of "enable DMA" option that is used to do dma transfers from host to fpga ?
2. once i enable this HPTXS port , i have to select - no. of pages and size of each page (on what basis should i select these two parameters) ?
3. how address mapping concept differs from maintaining descriptors table space, instantiating descriptor controller etc., (i think i asked 1 and 2 questions in otherway) ?
regards,
Anil
please suggest me a reference design on stratix 10 board with a PCIe , enabled high performance burst interface (HPTXS) port of 256 bit width.
I searched on the net to have a clear understanding about this port, but not found anything. But, there are 2 paras of information available on the user-guide that available from the tool, but didn't understood.
someone please send me a link to understand the functionality of that port, referral design.
some questions
1. can i enable this HPTXS port irrespective of "enable DMA" option that is used to do dma transfers from host to fpga ?
2. once i enable this HPTXS port , i have to select - no. of pages and size of each page (on what basis should i select these two parameters) ?
3. how address mapping concept differs from maintaining descriptors table space, instantiating descriptor controller etc., (i think i asked 1 and 2 questions in otherway) ?
regards,
Anil