Redundancy analysis algorithm

[mtdanaras]

I need a help to write vhdl code for redundancy analysis algorithm.

 

[TrickyDicky]

tell us the problem, we'll help

 

[mtdanaras]

Golomb compression

"library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;




entity fpdiv is
port (

en : out std_logic;
clkx8 : in std_logic;
reset : in std_logic;
A: in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);

c_dataut STD_LOGIC_VECTOR(2 downto 0);
clk: in STD_LOGIC;


data_out: out STD_LOGIC_VECTOR (3 downto 0)
);
end fpdiv;


architecture fpdiv_arch of fpdiv is

signal REMAINDERS0 : STD_LOGIC_VECTOR (5 downto 0);
signal REMAINDERS1 : STD_LOGIC_VECTOR (5 downto 0);
signal REMAINDERS2 : STD_LOGIC_VECTOR (5 downto 0);
signal REMAINDERS3 : STD_LOGIC_VECTOR (5 downto 0);

signal DIVISORS0 : STD_LOGIC_VECTOR (5 downto 0);
signal DIVISORS1 : STD_LOGIC_VECTOR (5 downto 0);
signal DIVISORS2 : STD_LOGIC_VECTOR (5 downto 0);
signal DIVISORS3 : STD_LOGIC_VECTOR (5 downto 0);

signal Q_TEMP : STD_LOGIC_VECTOR (3 downto 0);
signal Z0 : STD_LOGIC_VECTOR (2 downto 0);
signal Z1 : STD_LOGIC_VECTOR (2 downto 0);
signal ZERO : STD_LOGIC;

signal oe1,oe2,oe3,oe4,oe5,oe6,oe7,oe8,oe9 :std_logic;
signal d1,d2,d3,d4,d5,d6,d7,d8,d9 :std_logic_vector(22 downto 0);
signal w1,w2,w3,w4,w5,w6,w7,w8,w9 :integer range 0 to 23;


function sqrt ( d : UNSIGNED ) return UNSIGNED is
variable a : unsigned(31 downto 0):=d; --original input.
variable q : unsigned(15 downto 0):=(others => '0'); --result.
variable left,right,r : unsigned(17 downto 0):=(others => '0'); --input to adder/sub.r-remainder.
variable i : integer:=0;
begin
for i in 0 to 15 loop
right(0):='1';
right(1):=r(17);
right(17 downto 2):=q;
left(1 downto 0):=a(31 downto 30);
left(17 downto 2):=r(15 downto 0);
a(31 downto 2):=a(29 downto 0);
if ( r(17) = '1') then
r := left + right;
else
r := left - right;
end if;
q(15 downto 1) := q(14 downto 0);
q(0) := not r(17);
end loop;
return q;
end sqrt;


begin
Z0 <= (others => '0');
Z1 <= (others => '0');
DIVISORS0 <= Z0 & B(2 downto 0);
REMAINDERS3 <= Z1 & A(2 downto 0);

DIVISORS1 <= DIVISORS0(4 downto 0) & '0';
DIVISORS2 <= DIVISORS1(4 downto 0) & '0';
DIVISORS3 <= DIVISORS2(4 downto 0) & '0';

Q_TEMP(0) <= '1' when (REMAINDERS1 >= DIVISORS0) else '0';
Q_TEMP(1) <= '1' when (REMAINDERS2 >= DIVISORS1) else '0';
Q_TEMP(2) <= '1' when (REMAINDERS3 >= DIVISORS2) else '0';
Q_TEMP(3) <= A(3) xor B(3);

REMAINDERS2 <= REMAINDERS3 - DIVISORS2 when Q_TEMP(2) = '1' else REMAINDERS3;
REMAINDERS1 <= REMAINDERS2 - DIVISORS1 when Q_TEMP(1) = '1' else REMAINDERS2;
REMAINDERS0 <= REMAINDERS1 - DIVISORS0 when Q_TEMP(0) = '1' else REMAINDERS1;

ZERO <= '1' when B(2 downto 0) = Z1 else '0';

data_out <= (others => '0') when ZERO = '1' else Q_TEMP;

process(clkx8,reset,a,clk)
begin
if reset='0' then
oe1<='0';oe2<='0';oe3<='0';oe4<='0';oe5<='0';oe6<='0';oe7<='0';oe8<='0';
d1<=(others=>'0');d2<=(others=>'0');d3<=(others=>'0');d4<=(others=>'0');d5<=(others=>'0');
d6<=(others=>'0');d7<=(others=>'0');d8<=(others=>'0');
w1<=0;w2<=0;w3<=0;w4<=0;w5<=0;w6<=0;w7<=0;w8<=0;
en<='0';


elsif clkx8'event and clkx8='1' then
oe1<=oe2;oe2<=oe3;oe3<=oe4;oe4<=oe5;oe5<=oe6;oe6<=oe7;oe7<=oe8;oe8<=oe9;
d1<=d2;d2<=d3;d3<=d4;d4<=d5;d5<=d6;d6<=d7;d7<=d8;d8<=d9;
w1<=w2;w2<=w3;w3<=w4;w4<=w5;w5<=w6;w6<=w7;w7<=w8;w8<=w9;
en<=oe1;


end if;
if (clk<='1' and a=00000000) then
c_data<="000";
if (clk<='1' and a=00000001) then
c_data<="001";
elsif (clk<='1' and a=00000010) then
c_data<="010";
elsif (clk<='1' and a=00000011) then
c_data<="011";
elsif (clk<='1' and a=00000100) then
c_data<="100";
elsif (clk<='1' and a=00000101) then
c_data<="101";
elsif (clk<='1' and a=00000110) then
c_data<="110";
elsif (clk<='1' and a=00000111) then
c_data<="111";
end if;
end if;
end process;
end fpdiv_arch;"

This is the coding for Golomb Compression. But i dont get output for c_data. Plz correct my error and i need the output for c_data.
i run this coding using Modelsim Altera 6.4a simulator.

 

[TrickyDicky]

and where is the testbench code?

Secondly, whats with the second bit of the code?

if (clk <= '1' and a = 000000) then etc..

you cannot check if the clk is less than or equal to one. You SHOULD NOT be using the clock in logic, other than checking for rising edge.

 

[mtdanaras]

What i hav to do for getting c_data

 

[mtdanaras]

Plz give me VHDL coding for golomb compression

 

[TrickyDicky]

Sorry - Im out of golomb compression. Have you tried opencores.org