i hav vhdl code for aes encryption/decryption which runs fine during behavioral simulation. most parts of the algorithm are implemented using look up tables.
the synthesis went on running................... after a day's wait it got synthesised, but slice LUTs were overutilized.
similar to software, in hardware is there any means to free up and reuse some latches, once its initial function is done ?
First try to map your LUTs (AES SBOXes) to the FPGA RAMs it will reduce logic. If it will not help you can always optimize AES core.
You can design 10, 20, 40 ... clock cycle core depends on your performance.
deepa, you have to code sbox in such a way that RAM on FPGA gets inferred or instantiate RAM on FPGA and use it to program sbox. Here is one link that might be useful to start
i hav vhdl code for aes encryption/decryption which runs fine during behavioral simulation. most parts of the algorithm are implemented using look up tables.
the synthesis went on running................... after a day's wait it got synthesised, but slice LUTs were overutilized.
similar to software, in hardware is there any means to free up and reuse some latches, once its initial function is done ?
Hi!
i have implemented AES encrytption and decryption using verilog. I have simulated the result of encryption module, the problem that i am facing is in the simulation of Decryption module.How can i get the correct result?
Thanks
First try to map your LUTs (AES SBOXes) to the FPGA RAMs it will reduce logic. If it will not help you can always optimize AES core.
You can design 10, 20, 40 ... clock cycle core depends on your performance.
I'm trying to find a way to map my LUTs to RAM, but still I couldn't ..
Tareq suggested to do so by inferring BRAM or DRAM .. but this is not a solution, because my logic is not initially a RAM .. I just want to MAP my logic to unused RAM blocks ..
So, any help ? .. do u know how this can be done Syswip ?
Are you talking about large LUTs, as utilized in the said AES core, or regular logic elements that are implemented as small 4 or 6-input LUTs in FPGA? The latter can't be effectively mapped to internal RAM, I fear.
Are you talking about large LUTs, as utilized in the said AES core, or regular logic elements that are implemented as small 4 or 6-input LUTs in FPGA? The latter can't be effectively mapped to internal RAM, I fear.