I am working on an Ethernet Parser. I have faced a problem in synthesizing my designs. The Net delay is more more bigger than logic delay (as shown in pictures) !!! Is it possible to reduce the net delay???
Let me answer your question with a question: Your net delay is greater than your logic delay; so what? Does your design meet timing? If so, don't worry about it. You probably just have a long route to a register.
I seem to remember you've been told before to constrain your design.
Note the heading of the aforementioned net is an unconstrained setup path, with infinite slack, so yeah expect the route delay to be huge compared to the logic delay.
Also you should know that at the current process nodes for ICs the delay for routing is much much greater than the propagation delay for a logic gate. This used to be the other way around back when I started.
Let me answer your question with a question: Your net delay is greater than your logic delay; so what? Does your design meet timing? If so, don't worry about it. You probably just have a long route to a register.
Without a constraint the tool will put little effort into the routing. It will just place two luts somnewhere and a route between and then thinks its finished.
With a constraint, it will place the two luts and the route, and then replace/re-route if it didnt meet timing the first time (with how many re-attempts based on project settings).
Besides timing constraints you need a suitable design structure that has a certain chance to achieve timing closure at the intended clock frequency, e.g. by using pipiline registers.