Hi all,
I have one doubt regarding recovery and removal time. As par as I know we should assert reset asynchronously and de-assert it synchronously,
But what happens when the clock edge and reset(usually active low) both are active(i.e clock pos edge and reset is low) at a time? Will it not cause meta stability?
One more doubt is there any chance of having negetive recovery and removal time?
Please clarify me on this...
Thanks in advance,
Srini
Hi Srini,
Ur assumption of "assert reset asynchronously and de-assert it synchronously" is incorrect..then there is no meaning of asynchronous reset.
Recovery and removal timing checks ensure there is no metastability issue when you come out of reset (low-> high).
Removal Timing Check:
A removal timing check ensures that there is adequate time between an
active clock edge and the release of an asynchronous control signal. The
check ensures that the active clock edge has no effect because the asynchronous
control signal remains active until removal time after the active clock
edge. In other words, the asynchronous control signal is released (becomes
inactive) well after the active clock edge so that the clock edge can have no
effect
Recovery Timing Check:
A recovery timing check ensures that there is a minimum amount of time
between the asynchronous signal becoming inactive and the next active
clock edge. In other words, this check ensures that after the asynchronous
signal becomes inactive, there is adequate time to recover so that the next
active clock edge can be effective. For example, consider the time between
an asynchronous reset becoming inactive and the clock active edge of a
flip-flop. If the active clock edge occurs too soon after the release of reset,
the state of the flip-flop may be unknown.