A signal is crossing one clock domain and its feed to 2 other clock domains which are working on same clock.(fanout to 2 different domains)
like: clk1 to clk2,
clk1 to clk3.
and clk2= clk3
following are some cases: please provide your views on those-
1: after synchronization in another domains(clk2=clk3) signal is going to feed to a select line of mux, will it make any issue like reconvergence?
2: after synchronization in domains of same frequencies, synchronized signals are given to inputs of and gate, will it create any issue in design?
3: when both clk frequencies are different clk2 != clk3, what will happen in case 1 and case 2, how it will effect?