reconvergence of clock domain signals

[rajev_v]

a signal is crossing clock domain and its fanout to another2 domain that are working on same clock. and then after following are some cases: please provide your views

1: after synchronization in another domains signal is going to select line of mux, will it make any issue like reconvergence?

2: output of both same faned out to 2 domians (same clock) are and gated, this is case of reconvergence, will there be any issue if
a) both faned out domain are same clock driven or
b) both fandout domain are separate clock driven.

 

[ThisIsNotSam]

I can't understand this post at all. Please add a diagram or at least revise your text.

 

[rajev_v]

A signal is crossing one clock domain and its feed to 2 other clock domains which are working on same clock.(fanout to 2 different domains)
like: clk1 to clk2,
clk1 to clk3.
and clk2= clk3
following are some cases: please provide your views on those-

1: after synchronization in another domains(clk2=clk3) signal is going to feed to a select line of mux, will it make any issue like reconvergence?

2: after synchronization in domains of same frequencies, synchronized signals are given to inputs of and gate, will it create any issue in design?

3: when both clk frequencies are different clk2 != clk3, what will happen in case 1 and case 2, how it will effect?

 

[dpaul]

I also found it difficult to comprehend your #1. Now as I understand it...

A signal in clk1 domain goes to 2 other clock domains which are clk2 and clk3. We have clk2=clk3. So So we essentially have 2 clock domains in this discussion.

Now if you properly sync the signal coming out of clk1 (and going to clk2 or clk3) then it should not create any issues at clk2/clk3.
Make sure that the signal coming out of clk1 is an o/p of a flop and not from some combi logic (if it doesn't exist then it must of added in RTL). Also the o/p of sync flops should be feeding to any gates/muxes/etc at clk2/clk3 domain.

**broken link removed**

If clk2 != clk3, then you have to SEPARATELY sync your signal coming from clk1.

 

[ThisIsNotSam]

1 - if you are truly doing synchronization, no issue will occur. are you using FIFOs or some form of handshake?
2 - no, if 1 is done correctly.
3 - you have to add separate FIFOs for each.