Configuration bitstream loading. The duration of this event, named TBITLOAD for convenience, is a function of device family, density, configuration clock frequency, and configuration data port width. Consult the relevant device data sheet for more information.
In general:
TBITLOAD = (Bitstream Length in bits) / ((Clock Frequency in Hz) * (Configuration Port Width in bits))
When using a configuration clock derived from a crystal oscillator, the nominal clock frequency can be used in the calculation. When the configuration clock is derived from a ring oscillator or other highly variable source (for example, the Spartan-3 Generation FPGA is using a “master” configuration mode), use the guaranteed minimum clock frequency in the calculation.
There is an entire table dedicated to Configuration Clock (CCLK) Characteristics, which can be programmed during bitgen - each setting's min & max values encompass a fairly wide range due to process and other variations.