Reconfiguration time in FPGA.............

[pinkyvidya]

Can anyone help me in finding reconfiguration time in any FPGA?? I need a general equation to calculate the NETLIST RECONFIGURATION TIME for a system designed in hardwareand implemented in any fpga........Please help me..It is very urgent..........

Thank in advance............

 

[mux_master]

Do you mean the amount of time it takes to configure the FPGA? This will depend on the configuration method you are using, the size of the bitstream, and a few other factors. The user guide for your particular FPGA will have more details.

 

[pinkyvidya]

Thank you for your reply....But I think irrespective of the FPGA we are using there is some equation based on the size of netlist to find out the reconfiguration time....Kindly help me out with that.......

 

[mux_master]

Well the FPGA type determines the size of the configuration file. Larger FPGAs have larger configuration files. It also depends on how you will configure the FPGA. If you are using a serial loader from a SPI flash device, then the reconfiguration time just depends on the number of bits and the bit time. A parallel load could be faster.

 

[bigdogguru]

Mux_Master is correct the reconfiguration time of a FPGA is dependent on many variables, the issue is so complex several papers have been devoted solely to this topic:

Reconfiguration Time Aware Processing on FPGAs, Dittman and Gotz - PDF



Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing, Hindawi - PDF

Reconfiguration Time is of vital concern to the field of Reconfigurable Computing, a search on the topics will yield an abundance of papers and articles. A suboptimal approach would be to synthesize a worst case design record the bitstream download and startup times for your FPGA device. Partial reconfiguration of some devices is possible which yield low reconfiguration times, methods used in current reconfigurable systems.

 

[pinkyvidya]

Thanks for the information.........But I would like to know if there is any equation to in which the netlist size can be given as a parameter to calculate the run-time reconfiguration time in an FPGA...........That will be very helpful for me............

 

[bigdogguru]

That's a little like asking for an equation to calculate production time of a vehicle based on the number of bolts holding each wheel on. Sure the number of bolts has an impact on production time, especially if it's an eighteen wheel, but there are many other factors involved.

Xilinx Engineer quote, when asked a similar question:

It depends on the bitstream size, the configuration method, configuration clock rate, and other details.

Check out the PDFs:

Powering and Configuring Doc for Spartan 3



Based on Spartan 3 architecture:

Configuration bitstream loading. The duration of this event, named TBITLOAD for convenience, is a function of device family, density, configuration clock frequency, and configuration data port width. Consult the relevant device data sheet for more information.
In general:

TBITLOAD = (Bitstream Length in bits) / ((Clock Frequency in Hz) * (Configuration Port Width in bits))

When using a configuration clock derived from a crystal oscillator, the nominal clock frequency can be used in the calculation. When the configuration clock is derived from a ring oscillator or other highly variable source (for example, the Spartan-3 Generation FPGA is using a “master” configuration mode), use the guaranteed minimum clock frequency in the calculation.

There is an entire table dedicated to Configuration Clock (CCLK) Characteristics, which can be programmed during bitgen - each setting's min & max values encompass a fairly wide range due to process and other variations.

Of course this is a very generalized estimate based on Spartan 3 family, you'll need to find the relevant PDFs for the FPGA family in your design to refine the equation to your application.