allanvv
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Recharacterizing SRAM IP at lower voltage?
I'm using ARM IP's SRAM memory compiler for IBM 130nm. It is only characterized for nominal voltage and some worst case corners. I'd like to scale VDD significantly since I only need a fraction of its specified performance at full voltage. I do have netlists and full layout view available, but there are no simulation testbenches. Is it feasible to try to recharacterize the SRAM performance manually based on just the netlists? This isn't for commercial production, so the characterization doesn't need to be 100% perfect.
I'm using ARM IP's SRAM memory compiler for IBM 130nm. It is only characterized for nominal voltage and some worst case corners. I'd like to scale VDD significantly since I only need a fraction of its specified performance at full voltage. I do have netlists and full layout view available, but there are no simulation testbenches. Is it feasible to try to recharacterize the SRAM performance manually based on just the netlists? This isn't for commercial production, so the characterization doesn't need to be 100% perfect.
