Reason behind different resource usage reports between synplify pro and premier?

[Sumathigokul]

Hi..
I used synplify pro and premier for synthesis to Microsemi-Proasic3 device. Since the HDL (verilog) code i used to both tools are same, am expecting them to get synthesized similarly. The resource usage report (.srr) generated by both tools are different. Syn. premier implements the logic using 65 core cells (some cells are implemented as OR2, NOR2) whereas syn.pro uses 49 core cells (uses different logic, not implemented as OR2 or NOR2). What is the reason behind this considerable difference among these core cells count??? Is there any option to change the implementation settings, so that both tools use same no of core cells (i.e implements same kind of logic in each core cells)???

 

[mrflibble]

Since you say synplify pro uses different logic cells ... Presumably due to the use of different logic cells. If synplify pro uses LUTs (LUT4 for example) as logic elements, then this will typically require a lower cell count than if you were to use only OR2/NOR2.

To be sure what is going on you should check the synthesis results.

 

[Sumathigokul]

Since you say synplify pro uses different logic cells ... Presumably due to the use of different logic cells. If synplify pro uses LUTs (LUT4 for example) as logic elements, then this will typically require a lower cell count than if you were to use only OR2/NOR2.

To be sure what is going on you should check the synthesis results.

Can we change the settings to make both the tools to synthesize similarly????

 

[TrickyDicky]

But the tools are not the same
One is "pro" and one is "premier"
I assume they come with different prices?

Why would expect the same results from a cheaper product?

 

[Sumathigokul]

Can we change the settings to make both the tools to synthesize similarly????

Though the synthesis tools i used are different, at last my design has to be implemented in the same target device. Even if the synthesis process differs, the subsequent steps like MAP, PAR of that vendor specific tool will be the same. So why do this difference happens in those tools???

 

[TrickyDicky]

Is the generated netlist completly identical? Filesize the same? CRC check the same?
Unless the files are completly identical, the FIT results will differ in the same Tool

The fitter/PAR will use a seed value to get the fit going. This is based on several factors, the main one being the code base. If you use the whole tool chain from the same vendor, changing a single constant will give you a completely different fit result. So any small changes in the synth are also going to affect the outcome.

So basically - 2 tools are most likely going to give you 2 completely different bit files for the same device.