I have a FPGA where I am doing sampling in voice using A/D. I encrypt the data and I send them to the receiver. My question is how do I synchronize the transmitter with the receiver so that it decrypts the correct data? Any ideas? I use AES-128.
I think the question had more to do with framing the incoming data so they can tell where the AES blocks are.
You should probably frame the AES blocks with some sort of encapsulation so you can tell where the blocks are (and you don't encrypt the encapsulation).
If blind decryption is needed, and if the AES mode allows, it should be possible to estimate which of the 128 different bit alignments is correct. decryption failures look like noise while success looks like your data. audio will have lower energy in 0hz and fs/2 because the analog frontend filters these out.
Step1 Make sure you're not using any form of AES like CipherBlockChaining (at least not until you know where you are in the chain)
Step2 Framing the data as outlined by #3 is a good place to start.
example
1234(AESword)4321-----1234(AESword)4321
where 1234 is a delimiter
Could you provide more information on your system please?
Step1 Make sure you're not using any form of AES like CipherBlockChaining (at least not until you know where you are in the chain)
Step2 Framing the data as outlined by #3 is a good place to start.
example
1234(AESword)4321-----1234(AESword)4321
where 1234 is a delimiter
Could you provide more information on your system please?