The datasheet could help you to pursuit the theoretical maximum frequency in your case.
Look at the switching characteristics for the datasheet. You will find not only the maximum DSP frequency, but also others blocks switching characteristics.
For example, for Artix 7, sped grade -2, I can see the maximum frequency is 550.66 MHz. BRAM, has a maximum frequency of 460.83 MHz, so if you need to use BRAM, this is your limit. But you may try to use SerDes, for example, to try to overcome this limit without the use of BRAM. Normal logic seems to support this frequency if optimized until on state-of-the-art (Max. CLB frequency is 1286 MHz)
I would suggest to break the big problem into smaller problems. You can make several small blocks (DSP itself, logic, RAM) and try to reach the maximum datasheet frequency for each block. Next step is connecting the blocks, checking the resulting frequency. If you reach a good result for 1 DSP, then try to go to n DSPs.