Reading string and setting register bits in Verilog

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prab97

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I have a few lines of strings consisting of 0s and 1s only, in a file for example:

00000000010000100000001111101000
00000000100001000000010010110000
00010000010001000000000000000000
01111000000000000000000000000000

Each line is 32 chars in size. I have to read each line, and in a loop I have to set a 32 bit register according to the character encountered. This is what I wrote:

Code Verilog - [expand]
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module readBIN;
    reg [8*32:1] data;
    reg [32:0] inst;
    integer file, n, i;
initial
begin
    file = $fopen("test.txt", "r");
    i=0;
    while(!$feof(file)) begin
        n=$fgets(data, file);
        if(data[(i + 1) * 8:i * 8 + 1] == "1") begin
            inst[i]=1;
        end
        else begin
            inst[i]=0;
        end
    end
    $write("%d", inst);
end
endmodule


The problem is that I get an error saying part-select must be constant. Now how do I solve this problem?
I should tell you that I am an absolute beginner in Verilog and know only 'Hello world' as of now.

Thanks!
 
Last edited:

look into using readmemb.
 
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    prab97

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Well, the "part-select must be constant" is actually pretty descriptive. You are trying to do a bit select on a bit vector. You do this bit select from bit number A to bit number B. But these A and B values must be a constant value (as opposed to a runtime variable like the i
integer). As permute suggested, you may want to look into readmemb. See for example: Modeling Memories And FSM Part - I

Also, thanks for actually using code / syntax tags on a first post! You'd be amazed at how few people use that. Regarding the "[" etc stuff ... did that creep in after you entered it? Looks a bit weird...
 
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    prab97

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mrflibble said:
Also, thanks for actually using code / syntax tags on a first post! You'd be amazed at how few people use that. Regarding the "[" etc stuff ... did that creep in after you entered it? Looks a bit weird...
Click to expand...

Yeah the square brackets got converted into #91 and #93 automagically.
Thanks permute and mrflibble. I'll try figuring out readmemb usage. I am good at C, C++ and Java but never ever worked with Verilog.
 

Funny, sounds like it's a bit buggy then. Because when I typed "[" and did a Preview Post, I noticed it changed it to a bracket. Must be a feature of the syntax tag...
 

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