prab97
Newbie level 2
I have a few lines of strings consisting of 0s and 1s only, in a file for example:
00000000010000100000001111101000
00000000100001000000010010110000
00010000010001000000000000000000
01111000000000000000000000000000
Each line is 32 chars in size. I have to read each line, and in a loop I have to set a 32 bit register according to the character encountered. This is what I wrote:
The problem is that I get an error saying part-select must be constant. Now how do I solve this problem?
I should tell you that I am an absolute beginner in Verilog and know only 'Hello world' as of now.
Thanks!
00000000010000100000001111101000
00000000100001000000010010110000
00010000010001000000000000000000
01111000000000000000000000000000
Each line is 32 chars in size. I have to read each line, and in a loop I have to set a 32 bit register according to the character encountered. This is what I wrote:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 module readBIN; reg [8*32:1] data; reg [32:0] inst; integer file, n, i; initial begin file = $fopen("test.txt", "r"); i=0; while(!$feof(file)) begin n=$fgets(data, file); if(data[(i + 1) * 8:i * 8 + 1] == "1") begin inst[i]=1; end else begin inst[i]=0; end end $write("%d", inst); end endmodule
The problem is that I get an error saying part-select must be constant. Now how do I solve this problem?
I should tell you that I am an absolute beginner in Verilog and know only 'Hello world' as of now.
Thanks!
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