Reading image in VHDL test code

[sheikh]

Hello Dears
I want a VHDL test code for reading an image and then view the processed one. I google it and know about the textio package but don't know how to use it exactly. please explain about it and about the type of images that vhdl test code can read or write.
Regards
Mostaa

 

[TrickyDicky]

textio package can only read text files. There are no specific ways to read data files in VHDL - it can depend on what simulator you are using. Reading image files is possible though, but unless you understand textio, you wouldnt have a chance at understanding the work around to get data files into VHDL for modelsim

So - what is it you dont understand about textio?

 

[sheikh]

Thanks TrickyDicky, I use ISE & modelsim. i read a sample code in this blog

http://vhdlguru.blogspot.se/2010/03/reading-and-writing-files-in-vhdl-easy.html

but in a pdf i read that for reading an image its format is important and also its value must convert to hex and ... so i just need to know the right way.
Regards
Mostafa

 

[TrickyDicky]

yes, if you want to make life easy, then convert your image file into a text file.

 

[K-J]

Hello Dears
I want a VHDL test code for reading an image and then view the processed one. I google it and know about the textio package but don't know how to use it exactly. please explain about it and about the type of images that vhdl test code can read or write.
Regards
Mostaa

You'll want to write two procedures. One for reading an arbitrary binary file, the other for writing the same. I would suggest the following package:

package pkg_FileIO is
    -------------------------------
    -- Define some basic data types
    -------------------------------
    subtype t_BYTE  is integer range 0 to 2**8 - 1;

    ---------------------------------------
    -- And arrays of those basic data types
    ---------------------------------------
    type arr_t_BYTE  is array(natural range <>) of t_BYTE;

    ----------------------------
    -- And a pointer to an array
    ----------------------------
    type ptr_arr_t_BYTE is access arr_t_BYTE;

    procedure Read_File(File_Name: in STRING; Data: out ptr_arr_t_BYTE; Length: out integer);
    procedure Write_File(File_Name: in STRING; variable Data: in ptr_arr_t_BYTE; Length: in natural; Write_Status: out BOOLEAN);

end pkg_FileIO;

Now that you have the interface to the procedures defined, you need to write the guts of the 'Read_File' and 'Write_File' procedures to do the reading and writing of files. While the VHDL language definition won't guarantee anything here, your particular simulator might work just fine if you define the low level bytes in the file to be:

        type bit_vector_file is file of bit_vector; 
        FILE InFile:                bit_vector_file;

Lastly, once you have your two procedures written, I would suggest creating a testbench to verify that the whole thing works. Below is a process that will accomplish that task

    process
        variable Read_Data: work.pkg_FileIO.ptr_arr_t_BYTE;
        variable Length:    natural;
        variable Write_Status:  BOOLEAN;
    begin
        work.pkg_FileIO.Read_File(In_File_Name, Read_Data, Length);
        work.pkg_FileIO.Write_File(Out_File_Name, Read_Data, Length, Write_Status);
        assert Write_Status
            -- coverage off
            report "OOPS!  File did not write correctly"
            severity ERROR;
            -- coverage on
        wait;
    end process;

 

[sheikh]

Thanks a lot Dear K-J. it is very useful.