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Reading Data from Text File to use as inputs in VHDL Design

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Hi fellow forum members,

As the title suggests, I need to read data from a data file, get the integer values, convert them to two's complement binary and use them as inputs in my VHDL design. My goal is to build a basic signal generator via BASYS2 board and DAC. My plan is to use matlab as an ideal signal sampler, get the functions' values(square, sine, cosine, sawtooth etc.) then get the values on VHDL, changing the output values according to frequency predetermined before, implement DAC design, upload it on FPGA and observe the signal on oscilloscope. So far, I have managed the matlab part and prepared my .dat files. But I can't manage to read them on VHDL. As I have been learning VHDL for just 2 months, I am very new to this and couldn't understand any code related to reading in VHDL so I need your help.

Also, I have questions about reading values from .dat files. Will I able to use these values in my VHDL design or is what i am trying to do is outright ridiculous? Also, when I want to change the signal, will I have to re-compile everything and recreate .bit file to use it in FPGA? or should I somehow put the data file in FPGA board and somehow try to read it from it?

Thank you for your help,

The question refers to the specific features of your design compiler.

In constrast to Verilog, where $readmemb and $readmemh are widely supported by synthesis tools, only some compilers support text_io functions for data import. Some have vendor specific data formats to import constant data to ROM blocks.

I expect, that your design compiler supports one or the other way. At worst case, you can generate constant arrays in VHDL text by Matlab or another tool.

You can do that in real tim with the ATYS board and it's tools' or you have to implement something like ->"virtual IO" or -> "logic analyzer interface" to get and sent data from / to the FPGA.

Thank you for your replies. After trying to work this out for a week, I, at last, gave up and installed my values directly in code to ROM of FPGA. I now have different problem with the design which I posted but thank you for your time.

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