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| library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity diffclock2 is
Port (
pad_p : in std_logic; -- differential pin p from sensor
pad_n : in std_logic; -- differential pin n from sensor
DLY_CLK : in std_logic; -- not sure what kind of clock to supply here
dly_cnt : in std_logic_vector(4 downto 0); -- delay value from 0 to 31
dly_ld_clk : in std_logic; -- tells IDELAYE2 to load value in dly_cnt as the new delay value
dly_reset : in std_logic;
dly_refclk : in std_logic; -- 200mhz clock
CLK_OUT : out std_logic -- output delayed clock
);
end diffclock2;
architecture behavioral of diffclock2 is
signal CLK_IBUFG : std_logic;
signal CLK_DLY : std_logic;
signal CLK_BUFR : std_logic;
begin
clk_ibufg_I: IBUFGDS -- ** converts differential pin pair into single clock pin **
generic map (
IOSTANDARD => "LVDS_25",
DIFF_TERM => true
)
port map (
I => pad_p,
IB => pad_n,
O => CLK_IBUFG
);
clk_idelay_I: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE",
DELAY_SRC => "IDATAIN",
HIGH_PERFORMANCE_MODE => "FALSE",
IDELAY_TYPE => "VAR_LOAD",
IDELAY_VALUE => 0,
PIPE_SEL => "FALSE",
REFCLK_FREQUENCY => 200.0,
SIGNAL_PATTERN => "CLOCK"
)
port map (
CNTVALUEOUT => open,
DATAOUT => CLK_DLY, -- delayed clock
C => DLY_CLK,
CE => '0',
CINVCTRL => '0',
CNTVALUEIN => dly_cnt,
DATAIN => '0',
IDATAIN => CLK_IBUFG, -- input clock from differential pins on sensor
INC => '0',
LD => dly_ld_clk,
LDPIPEEN => '0',
REGRST => dly_reset
);
csi_CLK_BUFR: BUFR -- not sure why i need this
generic map (
BUFR_DIVIDE => "BYPASS",
SIM_DEVICE => "7SERIES"
)
port map (
O => CLK_BUFR,
CE => '1',
CLR => '0',
I => CLK_DLY
);
-- ** i think i need DDR in here somewhere too?? **
CLK_OUT <= CLK_BUFR;
idelayctrl_I: IDELAYCTRL
port map (
RDY => open,
REFCLK => dly_refclk, --200mhz input clock
RST => dly_reset
);
end behavioral; |