hi all,
how to assign the input data written in a file to the port, for testbench purpose using verilog hdl?
suppose i have some samples of input data written in .dat file,
and in my testbench i want to input all the values written in that file, how can i do it?
i have tried in the below manner and could not find any data assigned to the input pin while simulating,
$fopen will only open the file. To do any file operation in verilog this has to be done first. for reading from file try $memreadb (for binary files) or $memreadh (for hex files).
eg :
Code:
reg [7:0] mem[1027:0];
......
initial
begin
$readmemb("file_name",mem);
end
U also have $fscanf, $fgetc, $fread to read files. Not sure abt the exact syntax for their usage, but should be similar to above one.
thanks for the example code nand gates....however i tried it and gave me errors so i tried making changes. Firstly for me an 'always' worked before the @(posedge clk) statement. Even after making this change it keeps giving me errors. Can someone please help me debug?
Hi all if any body implemented dwt image processing using verilog can u just send me the architecture and fsm design(if possible) or tell me how to start the coding part.please help me in that.