voho
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reedback of the virtex
Hi all
Configuration is the process of loading a design bitstream into the FPGA internal configuration memory. Readback is the process of reading that data.
If somebody has always doing this in vhdl reading data in virtex II
Thank's regards
Hi all
Configuration is the process of loading a design bitstream into the FPGA internal configuration memory. Readback is the process of reading that data.
If somebody has always doing this in vhdl reading data in virtex II
Thank's regards