Re: help with simulation of the code

[kakarala]

Re: help with simulation of the code

Hi

I am trying to simulate the code for dct 8*8 which i found , i created a testbench an gave a set of inputs but i am not able to get the output. I am attaching the code and the testbench i used,

Thanks,

 

[nachumk]

Re: help with simulation of the code

Quick answer... You are not asserting reset. For an actual FPGA this MIGHT be OK, but for simulation it will cause Xs in the module and this will stop it from working. In the example I included below, output could be OK since as soon as a clock occurs output gets set to 0. But output will never get set to 1 since "xxx" (the value of count without reset) + "001" will be equal "xxx". And "xxx" will never be equal to "111".

That's it. Modelsim (and I'm guessing other simulators) will propagate uninitialized values.

PS - in synthesis this will work since count will either be turned on as 0s or 1s, and even IF they were "uninitialized and random" the 3 bits of count can still ONLY be 0s or 1s. There is no such thing as Xs in a synthesized FPGA.

Simple example:
signal output : std_logic;
signal count : std_logic_vector(2 downto 0);
if(rst = '1') then
output <= 0;
count <= 0;
elsif(rising_edge(clk)) then
output <= 0;
count <= count + "001";
if(count = "111") then
output <= 1;
end if
end if