rcx extraction problem in 90nm technology

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delay in 90 nm

Hi All,

How can I calculate typical basic gate delay for 90nm and 45 nm technology.
Can anyone suggest materail or approaches for the same. My aim is to calculate a encoder circuit delay in 90nm and 45nm technology implemenattion.


Pl. help me
 

90nm spice load

I am very unclear what you want.
You want to calculate the delay in a particular circuit in 90nm and 45 nm but for which foundary???
The gate dealys for a library is provided by the vendor which you can easily find out by openng the sdf file in any text editor. But I am not sure what is the problem if you explain with more details , I may be able to help.
 

90nm spice

Sorry for the confusion. I will explain my problem in a detailed manner. We have magma tool eith 130nm TSMC libarry. But i have to calculate the delay of one deoder circuit for 90nm technology. If I kbnow the gate then I can calculate the Total delay of the circuit. So is there any method to calculate the basic gate delay TSMC90nm tecnology or using spice ( I have 90nm model). I hope it is clear 4 u



 

for 45nm what do be the interconnect delay

Hi,
Basic gate delay will be of an invertor you can open the .lib and check the delay values for invertor.

But you will get only were approx delay.
If you know your decoder circuit pin functionality, you can find the exact delays by using spice.
--Dump spice netlist for your decoder.
-- Give the input stimulus
--plot the nodes where you want to check the delay.
See the wave form and calculate the delay . 50% of rise transition from input node to the node you wantr to calculate.
Please let me know if you have any questions.

--Arimilli Rajesh.
 

spice gate delay

Hi,

Ur explanation is lcear for me. But this delay and EDA tool delay calculaion need not be same. Anyway I will try with spice. BTW do you have any idea abt the interconnect delay analysis using spice. There r transmission line model in spice but will it be suitable for long onchip interconnect modelling.
Pl. give me more feedback, directions and materail for this

with thanks

 

spice example and 90nm

Hi,
EDA tools generally manipulate using the data from .lib which delays are from spice simulations.
Lets say in your libary u calculated the delays for 100ff and 300ff ,if the tool see the load of the cell is 200ff ,it manipulates using some alogorithms using the values of 100ff and 300ff to get the delays of 200ff LOAD.

You can get the extraction of RC using assura rcx and add this in your spice netlist and do the simulation.
Hope this helps.

-Arimilli Rajesh.
 

delay fo4 90nm

you use report area of your decoder to know how many cells are there in decoder and what type of cells.. and, or, xor,etc..
you read the library ventor documentation attached with your lib and lef files.. in that pdf you can see the delays of each standard cell.. thus by seeing schematics.. and from timing analysis you can see the critical path and just note the cells in that critical path.
by totalling delays of each cell in critical path you can get your decoder delay..

regards
shankar
 

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