i want to use random function in verilog HDL. i will have a set of numbers(6-8 in number) from which a random number has to be selected every time. suggest me the ways of implementing it.
Oh yeah, if this is verilog and the randomization is purely for simulation, then you might want to use SystemVerilog for your testbench. SV has a lot more random goodness compared to the older verilog standard. So if you use lets say Modelsim, then you should be good to go.