Random problem in Verilog..

[jelydonut]

Is there a way to seed the random function so every time the simulation is run a different set of random numbers is generated?

Everytime i run my testbench its generating the same random numbers everytime.. I tried to see if i could seed it with the system time somehow.. but am unable to find any info on it..

jelydonut

 

[bibo1978]

Random numbers are not truely random of course we all know that but you can use random generators for random time, you may use the Galios Function as a generator,

 

[jelydonut]

I'm assuming that you can't create different random numbers each time you run a simulation.. so i guess all i can do is pass in a seed and just use a different seed for different task calls in the bench.. does that sound like a safe assumption?

this way it easily creates reproducability but does not really create a random result each time a task is called..

jelydonut

 

[bibo1978]

in test bench you can do an asychronous seq. network with a random time delays "from random function" this way you may get a partially random results.
however your proposal seems O.K and will need less time.

 

[jelydonut]

Im not sure what you mean by a async seq. network..

Also, if the time delays are done from the random function wouldn't the time delays be identical every simulation run?

jelydonut

 

[bibo1978]

another technique is to use a random file to seed your random generator, I upload you a m-file that might help, of course you will need to run this m file every time before simulation, just to get various simulation results each time you run simulation. 'script it'