Random DC Voltage Source Simulation help needed

[mdtanvir100]

Hi there,

I am trying to simulate mismatch in a 10 bit D/A converter and unfortunately my PDK does not support Monte Carlo Simulation.

At least to simulate the threshold voltage mismatch I am trying to create a voltage source or a set of voltage sources which will generate random voltage each time I run the transient simulation in Cadence Spectre ADE.

Then I can connect the bias node to the random dc source and then to the gate of the current source to observe the threshold voltage effect.

It is a bit urgent for me to come up with the idea to do this. It would be great if you could advice me how can I do this in Cadence or by using Verilog A?

Regards,
Tanvir

 

[erikl]

You won't need random values for this type of simulation. Just use ± worst case values, and may be a few in between. Assign a parameter value to this/these voltage source(s), and change it/them via .ALTER commands.

 

[mdtanvir100]

Dear Erikl,

Thanks for your suggestions. Unfortunately I am noy familiar with Hspice. I am in a bit with time constraint and unable to explore Hspice.

Would you please tell me is there anything else in your mind ? May be with Verilog A?

Any kind of advice is appreciated.

Kind regards,

Tanvir

 

[dick_freebird]

See whether your simulator supports gauss() and
track() functions (the former, uncorrelated pseudo-
random; the latter, for correlated VT w/ process &
mismatches etc.).

If no, then consider something like simply inserting
voltage sources in series w/ gates, simple variables
that can be messed around in a nested loop-set to
bound, if not statistically model, the endpoints of
mismatch induced error.