dll_fpga
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RAMmodule ram (addr, clk, din, dout, we);
input [1 : 0] addr, din;
input clk, we;
output [1 : 0] dout;
reg[1:0] memory[3:0];
reg[1:0] dout_r;
always @(posedgeclk) begin
if (we)
memory[addr] <= din;
dout_r <= memory[addr];
endendmodule
I think the above code is a behavioral code of a ram.
How can we write a RTL code of a ram with an array of registers and a seperate address decoder .
How will the memory designers write the RTL of memories?or they write the behavioural model?
input [1 : 0] addr, din;
input clk, we;
output [1 : 0] dout;
reg[1:0] memory[3:0];
reg[1:0] dout_r;
always @(posedgeclk) begin
if (we)
memory[addr] <= din;
dout_r <= memory[addr];
endendmodule
I think the above code is a behavioral code of a ram.
How can we write a RTL code of a ram with an array of registers and a seperate address decoder .
How will the memory designers write the RTL of memories?or they write the behavioural model?