RAM: rising edge detection not working

[goodpranoy]

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ram_ent is
port(addr:in std_logic_vector(3 downto 0);
    addr_in:in std_logic_vector(3 downto 0);
    data_in:in std_logic_vector(7 downto 0);
    ram_write:in std_logic;
    enter:in std_logic;
clock:in std_logic;
ram_enable:in std_logic;
dout:out std_logic_vector(7 downto 0));
end ram_ent;

architecture ram_arch of ram_ent is
type ram_arr is array(0 to 15)of std_logic_vector(7 downto 0);
signal tmp_ram:ram_arr;
begin
process(clock,ram_enable,ram_write,enter)
begin
  if  ram_enable='1' and ram_write='0' then
if (clock'event and clock='1') then
dout<=tmp_ram(conv_integer(addr));
end if;
elsif ram_enable='1' and ram_write='1' then
if (clock'event and clock='1') then
if rising_edge(enter) then
tmp_ram(conv_integer(addr_in))<=data_in;
end if;
end if;
end if;

end process;
end ram_arch;

i wanted the data to be written to the ram only when there is a rising edge from the enter pin.( i've planned to use a push button ).
but when i simulated in modelsim, then it is not working as planned.
can anyone please tell me what is wrong in the program and also how to correct it.

thanks in advance.

 

[TrickyDicky]

All code should be inside the clocked part of the process, otherwise it is not a true clock enable. To do edge detection, you need to register the signal, and then compare this registered version to the new one.

 

[goodpranoy]

All code should be inside the clocked part of the process

sir isn't it so in the given program?
what all should be given inside?

sir, i didn't understand the next part.

can we use enter'event and enter='1' as we do for clock enable on rising edge?

 

[TrickyDicky]

You can only use one rising edge detect, as this becomes the clock input to the infered registers. Registers in FPGAs can only work on a single clock edge.

 

[goodpranoy]

k

so what should i do, if i want to write to RAM only at the rising edge of ENTER ?

 

[TrickyDicky]

register the enter signal, then check this register to the incoming version:

if rising_edge(clk) then
  enter_r <= enter;

  if enter = '1' and enter_r = '0' then --rising edge on enter
    --write to memory

 

[goodpranoy]

thank you.
helped me a lot.