RAM IPs in Equivalence Checking

[salma ali bakr]

Hi,

I'm doing Equivalence Checking between the RTL and the Netlist of a design, which has 4 RAM IPs. Of course, I can't use the behavioral HDL models of the RAMs since they're only used for simulations! So, what should I do now in order to verify the design?! Should I mark the RAMs as black boxes, or just use their interfaces?! Or maybe just load them as db files?! I'm totally confused about what I should do, and I've tried a lot with different scripts but in vain! So any ideas or sample scripts would be GREAT

By the way, I'm now using Synopsys Formality but I can switch to Cadence Conformal.

Thanks in advance and regards,
Salma

 

[bigmouthhua]

you can just set RAMs as BBox, since the RAM is analog macro which is validated by vendor.
what you need to verify in your design is the input/output value for RAMs.
Equiv check tools can push pattern to BBox to see if the golden & revised value of RAM input/output wires are equivalent.