Lego256
Newbie level 3
Hi here.
I was trying to design an OPA from the paper "Constant-gm Constant-Slew-Rate High-Bandwidth Low-Voltage Rail-to-Rail CMOS Input Stage for VLSI Cell Libraries" by Juan M. Carillo.
But I fear there is quite a problem in this paper. Considering the feedforward circuit Fig 2.b, it is claimed to cancel 1 gm0 in the middle of the input common mode range, and that i agree, but it's supposed to cancel 1 Ib as well, and that i don't. For me, the output DC current goes from 1 Ib to 3 Ib with the common mode voltage, it doesn't remain at 1 Ib as stated.
For my design, as I use a folded cascode load stage, the DC current variation would induce a bias variation that would be quite disturbing.
So, am I right, or am I mistaken? And if I'm right, can you think of a way to solve this? I thought of changing the bias voltage of the load stage (voltage on the gate of M7 and M8, Fig 5), i still wonder how to implement it...
Thanks !
Lego
I was trying to design an OPA from the paper "Constant-gm Constant-Slew-Rate High-Bandwidth Low-Voltage Rail-to-Rail CMOS Input Stage for VLSI Cell Libraries" by Juan M. Carillo.
But I fear there is quite a problem in this paper. Considering the feedforward circuit Fig 2.b, it is claimed to cancel 1 gm0 in the middle of the input common mode range, and that i agree, but it's supposed to cancel 1 Ib as well, and that i don't. For me, the output DC current goes from 1 Ib to 3 Ib with the common mode voltage, it doesn't remain at 1 Ib as stated.
For my design, as I use a folded cascode load stage, the DC current variation would induce a bias variation that would be quite disturbing.
So, am I right, or am I mistaken? And if I'm right, can you think of a way to solve this? I thought of changing the bias voltage of the load stage (voltage on the gate of M7 and M8, Fig 5), i still wonder how to implement it...
Thanks !
Lego
