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Low slew rate variable mark-space and frequency, astable multivibrator circuit needed

neazoi

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Hi,
I need a circuit of a low slew rate (leading and trailing edges), variable mark-space and frequency, astable multivibrator. It will operate from a few Hz to a few hundrend Hz
The multivibrator will be placed at the RF circuits of a receiver, so it has to have a low slew rate so as not to introduce harmonics and noise to it.

I can't find anything on the web, maybe you could help me.
 
Something like this using a DAC

1697629758676.png


The waveshape is derived from Excel sample table (which controls waveshape) and is input
to IDE (PSOC Creator) for the build. So you can shape it to your desired needs.

1697630397044.png


This is very simple design, maybe 10 lines code would suffice.

What else is onchip :

1697630501442.png


Regards, Dana.
 
If you want to limit the bandwidth (BW) , just add a low pass filter (LPF) to the Astable, PWM or Data Signal.

Bi-Phase is popular because of the ease of clock recovery. But when adding any filter, there is group delay which is the slope of phase shift vs f. This then causes data to have jitter (also known as) aka, ISI.

Designers will then choose a low Q "Raised-Cosine" LPF which in theory has zero ISI or sometimes just a Gaussian LPF or a linear phase filter. For such low frequencies, active filters are best and many free design tools exist.
 
IC's' seem designed to transition rapidly. (555 IC, op amps, logic gates, 7400 series). Instead to soften transitions it helps to reduce gain. An exception I've seen is the 4069 invert-gate unbuffered. On an oscilloscope I'v been able to achieve slow transitions.

Using discrete devices (mosfets) this circuit seems to qualify. A demo is in Falstad's menu of circuits, called CMOS inverter (slow transition). Capacitor integrator softens transitions. A side benefit is that a small change in clock duty cycle creates a large change of output duty cycle.

capacitor integrator softens clock transitions.png
 
Not sure I would do that with just a simple gate. Here I have 100 mV of noise
in system. Lots of jitter as one can see, and staying in active region of gate
thresholds because its G is not real high just aggravates the problem. Plus
hanging a large cap of a CMOS pin asking for trouble :



1697730029376.png



Regards, Dana.
 
Last edited:
1. Using the 74HC4049 as a linear inverter causes oscillation (noise) issues, unlike CD4049 due to higher speed and linear gain margin issues.
2. The triangle wave has harmonics attenuated by the 1st-order LPF used to make it oscillate. Although not stated, I would not be surprised to find that the filter requirements for a narrowband UHF data Tx look more like an 8th-order Bessell LPF.
3. Using the slow FET non-linear amplifier still has relatively high dV/dt for a "few hundred Hz BW."

The multivibrator will be placed at the RF circuits of a receiver, so it has to have a low slew rate so as not to introduce harmonics and noise to it.

I think this may be partly due to a high input Z sensitivity and unshielded signals. e.g. try coax or twisted pair magnet wire.
 
Last edited:
The Wien-bridge oscillator clips its output (sine waves) when not carefully adjusted. In the same manner it yields the slower slew rate.

I discovered this arrangement of potentiometers creates a wide range of frequencies. 100nF caps are suitable for low frequencies yet are not fussy about polarity as are large electrolyics.

wien-bridge oscil variable frequency (slow slew).png
 

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