pianomania
Member level 5
rs latch unstable
i use two NOR gate with its output feed into each other as a R-S latch , but why the result is unstable when the simulation step is bigger then 1ns ? what i use is analog simulator.
I mean if we input 0 into S , then the output should be unchanged, but the result will be changed sometimes. But why? it is because the reason of simulator or circuit?
i use two NOR gate with its output feed into each other as a R-S latch , but why the result is unstable when the simulation step is bigger then 1ns ? what i use is analog simulator.
I mean if we input 0 into S , then the output should be unchanged, but the result will be changed sometimes. But why? it is because the reason of simulator or circuit?