Quick question on non-overlapping clock generators

[diarmuid]

Hello All,

Im not so experienced with non-overlapping clock generators so have 2 probably quite basic questions on them:

Going by the topology of two cross-coupled NOR gates with even numbers of inverters inserted in their feedback paths:

- Are the inverters inserted to increase the non-overlapping durations?

- Could you not just use an inverter string consisting of an odd number of inverters instead?

Thanks and all the best,

Diarmuid

 

[dick_freebird]

You might see alternatives with NAND and odd # inverters.
The inverters set the majority of the nonoverlap dwell but
the phasing has to give the logic what it needs for the
active phase to be logically unique.

 

[diarmuid]

I done a bit more reading up on the subject and yes you are right, the degree of non-overlap is determined by the number of
inverters in the feedback chain (even for NOR, odd for NAND). More inverters increase non-overlap but at the cost of reduced
duty cycle.

However, what about just using an inverter string (consisting of an odd number of inverters)?

From sims I ran I see this produces small non-overlap. I get ~ 1ns non-overlap using an inverter string of 9 inverters. There
must be some snag to this that Im not seeing. Anything obvious?

Thanks,

Diarmuid

 

[dick_freebird]

So you've got ~ 100pS/stage prop delays; roughly right,
I guess, for a low fanout short channel technology. You
might add dummy loading to stretch the delay total without
unacceptable degradation to risetime / jitter. For long
nonoverlap times I will create a RC delay block (with
hysteresis for anti-chatter) with a couple inverters' worth
of squaring / boosting afterward, substituting this for a
much longer inverter chain. There's an area trade between
inverters and resistor / capacitor sizes that you want to
explore, in this decision.