Quick Poll: Variables in Synthesizable VHDL

[gliss]

Quick question:
Who uses variables in synthesizable VHDL?

 

[semiconductorman]

When u want to model the intermediate combinational logic u use variables ... .. hope this helps

 

[vomit]

I use variables for local stuff that is relevant to the process but should not be visible to other processes. Signals are at architecture scope, so they expose many process-local stuff unnecessarily.

process(clk)
variable v_Async_c,v_Async_c2 : std_logic;
begin
  if rising_edge(Clk) then

    if v_Async_c2='1' then ...
      ...
    end if;
    -- resynchronize asynchronous input without exposing temporary signals
    v_Async_c2:=v_Async_c;
    v_Async_c:=AsyncInput;
  end if;
end process;

Of course you should mind the order of assignment in this case, and it should be done clearly at the end of the process. Use before assignment infers a flipflop; assignment before use is a combinatorial net.

A decent choice of variable naming to indicate the presence of registers could help. I know people fear variables because of this, but we should not avoid a language feature because of fear, but instead find ways to deal with the extra intricacies of variables versus signals.

 

[linuxluo]

hi,
I think it's a good habit to not use variable in synthesizable vhdl. variable just like a something in C/C++, but not like a signal in real circuit.

 

[gliss]

"avoid a language feature "

But, were variables intended to be synthesizable? For modeling, I could see the benefit. Variable instances aren't always clear how they will be netlisted or realized. Unless coded very carefully, unexpected gates and nets will be made.
Also, what difference does it make if the signals are visiable to other processes? If those signals aren't driving other nets, does it matter?

 

[amraldo]

variables are used for intermediate values.
they may infer latches if:
1-they are used before assigned.
2-they are not mentioned in all branches of a conditional assignment.
for more details u can purchase VHDL synthesis primer by Bhsakr (not sure of authors name)

 

[Kulprashant]

hi,
variables are programmable objects we cannot access them outside.

with regards,
kul.

Added after 0 seconds:

hi,
variables are programmable objects we cannot access then outside.

with regards,
kul.

Added after 1 seconds:

hi,
variables are programmable objects we cannot access them outside.

with regards,
kul.